1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor Dynamic Random Access Memory (DRAM) device each memory cell of which has a stacked-capacitor structure, and a fabrication method of the device.
2. Description of the Prior Art
In recent years, the memory cell of DRAMs has been miniaturized more and more from generation to generation. Even if the memory cell is minimized, a specific charge is essentially stored in the storage capacitor of the cell to store the information.
The obtainable capacitance of the storage capacitor tends to decrease dependent upon the level of the miniaturization of the storage cell. On the other hand, the necessary capacitance of the capacitor is almost constant when the storing voltage to be applied across the capacitor is fixed. Therefore, it is necessary for the capacitor to compensate the capacitance decrease due to the miniaturization by, for example, increasing the surface area of the capacitor. This surface area increase has been popularly realized by increasing the thickness of the lower electrode (or, storage electrode) of the capacitor.
However, the thickness increase of the lower or storage electrode of the capacitor causes an excessive height difference between the memory cell area where the memory cells are arranged in a matrix array and the peripheral circuit area where the peripheral logic circuits for driving the memory cells are formed. As a result, an aluminum (Al) wiring layer which is formed over the memory cell area and the peripheral circuit area tends to have some excessively thin parts and/or to be partially broken.
Also, in the pattering step of the wiring layer, a photoresist film on the aluminum layer is patterned by using a photolithography process to thereby form an etching mask. The increased overall height of the capacitance causes an excessive focal point shift between the area located over the capacitor and the remaining area during the photolithography process. As a result, the patterning accuracy of the wiring layer will degrade.
Such the height difference as above can be relaxed or decreased by, for example, forming a thick interlayer insulating layer to cover the storage capacitors over the entire semiconductor substrate and then planarizing the surface of the interlayer insulating layer thus formed by a thermal reflowing process or Chemical-Mechanical Polishing (CMP) process. However, the thick interlayer insulating layer will cause another problem of disconnection or breaking of the aluminum wiring layer within contact holes. The reason is that the contact holes formed through the thick interlayer insulating layer have a large aspect ratio, which is defined as a ratio of the height of the holes with respect to the width/diameter of the holes. This results in degradation in step coverage of the aluminum wiring layer.
Then, to solve the above problem of disconnection or breaking of the aluminum wiring layer within the contact holes, an improved conventional structure where conductive pads for the capacitors are formed by using a conductive layer for forming the lower storage electrode of the capacitor was proposed. This conventional structure was disclosed in the Japanese Non-Examined Patent Publication No. 3-270168 published in December 1991.
The fabrication method of the conventional structure of the DRAM is explained below with reference to FIGS. 1A to 1F.
It is needless to say that this conventional DRAM has a lot of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and a lot of stacked capacitors in a memory cell area and a lot of MOSFETs in a peripheral circuit area. However, for the sake of simplification of description, only two of the MOSFETs and only two of the corresponding capacitors in the memory cell area and only one of the MOSFETs in the peripheral circuit area is explained here.
First, as shown in FIG. 1A, a field oxide layer 102 is selectively formed on a main surface of a p-type single-crystal silicon (Si) substrate 101 by a popular LOcal Oxidation of Silicon (LOCOS) process, thereby defining active regions in the surface area of the substrate 101 in the memory cell area A1 and the peripheral circuit area A2. The main surface of the substrate 101 is exposed from the field oxide layer 102 in the active regions.
Next, after impurity ions are selectively implanted into the active regions to adjust the threshold voltage of the MOSFETs, gate oxide layers 103 are selectively formed on the main surface of the substrate 101 in the respective active regions. An n-type polysilicon layer with a thickness of approximately 300 nm, which is doped with phosphorus (P), is formed over the entire substrate 101 by a popular Chemical Vapor Deposition (CVD) process. The n-type polysilicon layer is then patterned to form gate electrodes 104 on the corresponding gate oxide layers 103, and gate electrodes 104A on the field oxide layer 102.
Subsequently, using the gate electrodes 104 and the field oxide layer 102 as a mask, the active regions of the substrate 101 are selectively ion-implanted with phosphorus (P) with a dose of approximately 2.times.10.sup.13 atoms/cm.sup.2, thereby forming n.sup.- -type diffusion regions 105 used for source/drain regions of the MOSFETs. A layer of High-Temperature Oxide (HTO) of silicon is formed over the entire substrate 101 by a Low-Pressure CVD (LPCVD) process and is etched back by an anisotropic etching process, thereby forming sidewall spacers 106 on the exposed main surface of the substrate 101 and sidewall spacers 106A on the field oxide layer 102 at each side of the respective gate electrodes 104.
Next, using a patterned photoresist film (not shown), the sidewall spacers 106 and the gate electrodes 104 as a mask, the active regions of the substrate 101 in the peripheral circuit area A2 are selectively ion-implanted with arsenic (As) with a dose of approximately 3.times.10.sup.15 atoms/cm.sup.2, thereby forming n.sup.+ -type diffusion regions 107 used for source/drain regions of the MOSFETs. Thus, Lightly-Doped Drain (LDD) structures are formed in the active regions for the n-channel MOSFETs in the peripheral circuit area A2.
After removing the above patterned photoresist film, using another patterned photoresist film (not shown) covering the memory cell area A1 and the active regions for the n-channel MOSFETs thus formed, the sidewall spacers 106 and the gate electrodes 104 as a mask, the remaining active regions of the substrate 101 in the peripheral circuit area A2 are selectively ion-implanted with boron difluoride (BF.sub.2) with a dose of approximately 3.times.10.sup.15 atoms/cm.sup.2, thereby forming p-channel MOSFETs (not shown) in the peripheral circuit area A2.
Following this, a Boron-doped Phosphor-Silicate Glass (BPSG) layer 109 with a thickness of approximately 400 nm is formed by a CVD process over the entire substrate 101. The BPSG layer 109 serves as a first interlayer insulating layer located between the gate electrodes 104 and bit lines 108 which will be formed in the next step. The state at this stage is shown in FIG. 1A.
Further, as shown in FIG. 1B, the first interlayer insulating layer 109 is selectively etched to form a contact hole 110 vertically extending to the corresponding one of the n.sup.- -type diffusion regions 105 in the memory cell area A1. A patterned conductive layer 108 serving as the bit lines is then formed on the first interlayer insulating layer 109. The bit line 108 thus formed are contacted with and electrically connected to the corresponding one of the n.sup.- -type diffusion regions 105 in the memory cell area A1 through the contact hole 110.
Subsequently, a BPSG layer 111 serving as a second interlayer insulating layer is formed to cover the entire substrate 101 by a CVD process. The second interlayer insulating layer 111 and the underlying first interlayer insulating layer 109 are selectively etched to form contact holes 112 at corresponding locations to the n.sup.- -type diffusion regions 105 in the memory cell area A1 and contact holes 113 at corresponding locations to the n.sup.+ -type diffusion regions 107 in the peripheral circuit area A2.
To form lower or storage electrodes 115 of the capacitors in the memory cell area A1 and contact pads 116 in the peripheral circuit area A2, an n-type polysilicon layer with a thickness of approximately 600 nm, which is doped with phosphorus, is deposited on the second interlayer insulating layer 111 by a CVD process. Using a patterned photoresist film 114 formed on the n-type polysilicon layer thus formed as a mask, the n-type polysilicon layer is patterned to thereby form the lower or storage electrodes 115 and the contact pads 116. The state at this stage is shown in FIG. 1C.
After removing the photoresist film 114, a silicon nitride (Si.sub.3 N.sub.4) layer with a thickness of approximately 6 nm is deposited on the lower or storage electrodes 115, the contact pads 116, and the exposed second interlayer insulating layer 111 over the entire substrate 101. The Si.sub.3 N.sub.4 layer is then oxidized in a steam atmosphere at a temperature of 850.degree. C. for 30 minutes to thereby form a silicon dioxide (SiO.sub.2) layer with a thickness of approximately 1 nm in the surface area of the Si.sub.3 N.sub.4 layer. The combination of the Si.sub.3 N.sub.4 layer and the SiO.sub.2 layer thus formed serves as a common dielectric 117 of the capacitors, as shown in FIG. 1D.
An n-type polysilicon layer with a thickness of approximately 200 nm, which is doped with phosphorus, is then formed over the entire substrate 101 by a popular CVD process. Using a patterned photoresist film 118 formed on the common dielectric 117 as a mask, the n-type polysilicon layer thus formed is then etched to be selectively left in the memory cell area A1. If the gaseous mixture of carbon tetrachloride (CCl.sub.4) and oxygen (O.sub.2) is used as an etching gas, the polysilicon layer may be selectively etched while the common dielectric 117 made of the Si.sub.7 N.sub.4 and SiO.sub.2 layers is left substantially unchanged through this etching process in the peripheral circuit area A2.
Thus, a common upper or cell-plate electrode 119 of the capacitors is formed in the memory cell area A1 by the patterned, remaining n-type polysilicon layer. The state at this stage is shown in FIG. 1D. Each of the storage capacitors 120 is made of the corresponding lower or storage electrode 115, the common dielectric 117, and the common upper or cell-plate electrode 119.
Since the contact pads 116 in the peripheral circuit area A2 are formed by the same polysilicon layer as that of the lower or storage electrodes 115, the height of the pads 116 is almost the same as that of the capacitors 120, as shown in FIG. 1D.
After removing the patterned photoresist film 118, a BPSG layer 121 serving as a third interlayer insulating layer is formed to cover the entire substrate 101 by a CVD process. The third interlayer insulating layer 121 is then subjected to a heat-treatment in a nitrogen (N.sub.2) atmosphere at a temperature of approximately 900.degree. C., thereby planarizing the surface of the layer 121.
Using a patterned photoresist film 122 formed on the third interlayer insulating layer 121 as a mask, the layer 121 and the underlying dielectric 117 are selectively etched to form contact holes 123 exposing the underlying contact pads 116 in the peripheral circuit area A2, as shown in FIG. 1E. The contact holes 123 are located right over the n.sup.- -diffusion regions 107, respectively.
Finally, after removing the photoresist film 122, an aluminum layer is formed on the third interlayer insulating layer 121 to be patterned, thereby forming wiring conductors 124 contacted with and electrically connected to the corresponding contact pads 116, respectively.
Thus, the conventional DRAM with the stacked-capacitor structure is finished, as shown in FIG. 1F.
The conventional fabrication method of the DRAM as shown in FIGS. 1A to 1F, however, has the following problem.
When the polysilicon layer for forming the common upper or cell-plate electrode 119 of the capacitors 120 is selectively etched away in the peripheral circuit area A2, even if the gaseous mixture of carbon tetrachloride (CCl.sub.4) and oxygen (O.sub.2) is used as an etching gas, the obtainable selection ratio of this etching process will be approximately 100 at the highest. This etching process using the above mixture of CCl.sub.4 and O.sub.2 was explained in the book entitled "MOS LSI FABRICDATION TECHNOLOGY" on page 177-178, written by T. Tokuyama and N. Hashimoto, published by Nikkei McGraw-Hill Inc. in 1985.
In this case, as shown in FIG. 2A, to completely remove the polysilicon layer 125 used for the common upper electrode 119 of the capacitors within the narrow space or gap 130 between the adjacent contact pads 116, the necessary etching period will be approximately three times as long as that of the popular etching process where no such the narrow space or gap 130 exists or longer. The reason is as follows.
In FIG. 2A, the contact pads 116 have the same height of approximately 600 nm from the main surface of the substrate 101; in other words, the space or gap 130 between the adjacent pads 116 has a large depth of approximately 600 nm. Therefore, the part of the polysilicon layer 125 which is buried in the space 130 is very difficult to be etched away using the etching mixture of CCl.sub.4 and O.sub.2. This results in the long etching period.
The excessively long etching period badly affects the common dielectric 117. Specifically, even if the dielectric 117 having a small thickness of approximately 6 nm is able to withstand the etching force or action during the popular etching period, it is unable to withstand the etching force during the excessively long etching period. As a result, the dielectric 117 tends to be broken, thereby exposing the underlying pads 116 from the dielectric 117. In the worst case, the pads 116 themselves are also broken in addition to the dielectric 117, as shown in FIG. 2B.